From 031f396c71e750fede19651ba3a14e262a87e117 Mon Sep 17 00:00:00 2001
From: Matt Horsnell <Matt.Horsnell@arm.com>
Date: Thu, 17 Mar 2011 19:20:19 -0500
Subject: ARM: Fix RFE macrop.

This changes the RFE macroop into 3 microops:

URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset;         // optionally auto-increment
PC = URa; CPSR = URb;     // write to the PC and CPSR.

Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.
---
 src/arch/arm/intregs.hh | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/arch/arm/intregs.hh')

diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh
index 4b2cc560d..2cbed6c59 100644
--- a/src/arch/arm/intregs.hh
+++ b/src/arch/arm/intregs.hh
@@ -110,6 +110,8 @@ enum IntRegIndex
 
     INTREG_ZERO, // Dummy zero reg since there has to be one.
     INTREG_UREG0,
+    INTREG_UREG1,
+    INTREG_UREG2,
     INTREG_CONDCODES,
     INTREG_FPCONDCODES,
 
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