From 401165c778108ab22aeeee55c4f4451ca93bcffb Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Fri, 13 May 2011 17:27:01 -0500
Subject: ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
---
 src/arch/arm/intregs.hh | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/arch/arm/intregs.hh')

diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh
index 000c6306d..c26e36211 100644
--- a/src/arch/arm/intregs.hh
+++ b/src/arch/arm/intregs.hh
@@ -112,7 +112,9 @@ enum IntRegIndex
     INTREG_UREG0,
     INTREG_UREG1,
     INTREG_UREG2,
-    INTREG_CONDCODES_F,
+    INTREG_CONDCODES_NZ,
+    INTREG_CONDCODES_C,
+    INTREG_CONDCODES_V,
     INTREG_CONDCODES_GE,
     INTREG_FPCONDCODES,
 
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