From 2cac191491bbce22383d4fb81ea694e656b3c294 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 20 Aug 2019 10:48:34 +0100 Subject: arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regs The readMiscReg/setMiscReg methods were not forwarding register reads/writes to the cpu interface when in AArch32. Change-Id: Ide983e793b8033a88d31fe6ea87eaeffe9b093f5 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20611 Tested-by: kokoro Maintainer: Andreas Sandberg --- src/arch/arm/isa.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/arch/arm/isa.cc') diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 299698d3d..b95710506 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -737,6 +737,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: return getGenericTimer(tc).readMiscReg(misc_reg); + case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15: case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: return getGICv3CPUInterface(tc).readMiscReg(misc_reg); @@ -2069,6 +2070,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: getGenericTimer(tc).setMiscReg(misc_reg, newVal); break; + case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15: case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); -- cgit v1.2.3