From c1e1de8d69624b1cf18a13a46e624ad5827954b7 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 2 Jun 2010 12:58:16 -0500
Subject: ARM: Some TLB bug fixes.

---
 src/arch/arm/isa.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/arch/arm/isa.cc')

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 3fcd25fe5..8446962a2 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -215,6 +215,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
         break;
       case MISCREG_SCTLR:
         {
+            DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
             SCTLR sctlr = miscRegs[MISCREG_SCTLR];
             SCTLR new_sctlr = newVal;
             new_sctlr.nmfi =  (bool)sctlr.nmfi;
-- 
cgit v1.2.3