From 33bb1aa386fd6e6b4bc93797e129bc5c4baa6a36 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Thu, 22 Feb 2018 15:50:16 +0000
Subject: arch-arm: Created function for TLB ASID Invalidation

This patch is intended to avoid code duplication and extends the set of
TLBI ISA functions adding the entry invalidation by ASID match.

Change-Id: I9bcb498059ea480dd2118639c7b3c64fea80a5e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9181
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---
 src/arch/arm/isa.hh | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/arch/arm/isa.hh')

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index f36bc89ca..05d118c4d 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -404,6 +404,9 @@ namespace ArmISA
         void tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
                      uint8_t target_el);
 
+        void tlbiASID(ThreadContext *tc, uint16_t asid, bool secure_lookup,
+                      uint8_t target_el);
+
       public:
         void clear();
         void clear64(const ArmISAParams *p);
-- 
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