From 6aa229386dcd8b6d15529a0acdf8e3040dfeb337 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:08 -0500 Subject: ARM: Implement a function to decode CP15 registers to MiscReg indices. --- src/arch/arm/isa.hh | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/arch/arm/isa.hh') diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index c64f7bef9..080298158 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -152,6 +152,11 @@ namespace ArmISA cpsr.t = 0; return cpsr; } + if (misc_reg >= MISCREG_CP15_UNIMP_START && + misc_reg < MISCREG_CP15_END) { + panic("Unimplemented CP15 register %s read.\n", + miscRegName[misc_reg]); + } return readMiscRegNoEffect(misc_reg); } @@ -205,6 +210,11 @@ namespace ArmISA tc->setNextPC(npc); } + if (misc_reg >= MISCREG_CP15_UNIMP_START && + misc_reg < MISCREG_CP15_END) { + panic("Unimplemented CP15 register %s wrote with %#x.\n", + miscRegName[misc_reg], val); + } return setMiscRegNoEffect(misc_reg, val); } -- cgit v1.2.3