From 92abad849186256f4a4b309ed867d375d07c5c63 Mon Sep 17 00:00:00 2001 From: Jordi Vaquero Date: Tue, 6 Aug 2019 15:49:14 +0200 Subject: arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/isa.hh | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/arm/isa.hh') diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 63051cd83..5e337c223 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -95,6 +95,7 @@ namespace ArmISA bool haveGICv3CPUInterface; uint8_t physAddrRange; bool haveSVE; + bool haveLSE; bool havePAN; /** SVE vector length in quadwords */ @@ -687,6 +688,7 @@ namespace ArmISA SERIALIZE_SCALAR(physAddrRange); SERIALIZE_SCALAR(haveSVE); SERIALIZE_SCALAR(sveVL); + SERIALIZE_SCALAR(haveLSE); SERIALIZE_SCALAR(havePAN); } void unserialize(CheckpointIn &cp) @@ -704,6 +706,7 @@ namespace ArmISA UNSERIALIZE_SCALAR(physAddrRange); UNSERIALIZE_SCALAR(haveSVE); UNSERIALIZE_SCALAR(sveVL); + UNSERIALIZE_SCALAR(haveLSE); UNSERIALIZE_SCALAR(havePAN); } -- cgit v1.2.3