From 0ff71c7c343f2cb2ef4cb89168267795fda6ff15 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:11 -0500 Subject: ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers. --- src/arch/arm/isa/decoder/arm.isa | 15 +-------------- src/arch/arm/isa/decoder/thumb.isa | 2 +- 2 files changed, 2 insertions(+), 15 deletions(-) (limited to 'src/arch/arm/isa/decoder') diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index 6ead79c72..477a1ec60 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -159,20 +159,7 @@ format DataOp { } } // format FloatOp } - 0xa: decode MISC_OPCODE { - 0x1: decode MEDIA_OPCODE { - 0xf: decode RN { - 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); - 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); - 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); - } - 0xe: decode RN { - 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); - 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); - 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); - } - } // MEDIA_OPCODE (MISC_OPCODE 0x1) - } // MISC_OPCODE (CPNUM 0xA) + 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); 0xf: McrMrc15::mcrMrc15(); } // CPNUM (OP4 == 1) } //OPCODE_4 diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa index 23c33df48..9c64fd37a 100644 --- a/src/arch/arm/isa/decoder/thumb.isa +++ b/src/arch/arm/isa/decoder/thumb.isa @@ -86,7 +86,7 @@ default: WarnUnimpl::cdp(); // cdp2 } 0x1: decode LTCOPROC { - 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); + 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); default: decode CPNUM { 15: McrMrc15::mcrMrc15(); default: decode HTOPCODE_4 { -- cgit v1.2.3