From 432fa0aad6092d6a9252f6a9c83c8b36509c1341 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 8 Nov 2010 13:58:24 -0600 Subject: ARM: Add support for M5 ops in the ARM ISA --- src/arch/arm/isa/decoder/arm.isa | 8 +++++++- src/arch/arm/isa/decoder/thumb.isa | 3 ++- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/isa/decoder') diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index 3f43b23e1..9ab95b82f 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -90,7 +90,12 @@ format DataOp { 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse(); 0x2: ArmSignedMultiplies::armSignedMultiplies(); - 0x3: ArmMiscMedia::armMiscMedia(); + 0x3: decode MEDIA_OPCODE { + 0x1F: decode OPC2 { + default: ArmMiscMedia::armMiscMedia(); + } + default: ArmMiscMedia::armMiscMedia(); + } } } 0x4: ArmMacroMem::armMacroMem(); @@ -107,6 +112,7 @@ format DataOp { 0xa, 0xb: VfpData::vfpData(); } // CPNUM 1: decode CPNUM { // 27-24=1110,4 ==1 + 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); 0xf: McrMrc15::mcrMrc15(); } // CPNUM (OP4 == 1) diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa index d0f5b8646..f144e3003 100644 --- a/src/arch/arm/isa/decoder/thumb.isa +++ b/src/arch/arm/isa/decoder/thumb.isa @@ -84,6 +84,7 @@ decode BIGTHUMB { default: WarnUnimpl::cdp(); // cdp2 } 0x1: decode LTCOPROC { + 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); 0xf: McrMrc15::mcrMrc15(); } @@ -125,7 +126,6 @@ decode BIGTHUMB { 0x0: LoadByteMemoryHints::loadByteMemoryHints(); 0x1: LoadHalfwordMemoryHints::loadHalfwordMemoryHints(); 0x2: Thumb32LoadWord::thumb32LoadWord(); - 0x3: Unknown::undefined(); } } 0x1: decode HTOPCODE_8_7 { @@ -140,6 +140,7 @@ decode BIGTHUMB { default: WarnUnimpl::cdp(); // cdp2 } 0x1: decode LTCOPROC { + 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); 0xf: McrMrc15::mcrMrc15(); } -- cgit v1.2.3