From b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 2 Jun 2010 12:58:16 -0500
Subject: ARM: Implement ARM CPU interrupts

---
 src/arch/arm/isa/decoder/arm.isa | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/arch/arm/isa/decoder')

diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index 163da5ca0..467b98eaa 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -109,9 +109,10 @@ format DataOp {
 #endif
                 }
                 default: PredImmOp::msr_i_cpsr({{
+                            SCTLR sctlr = Sctlr;
                             uint32_t newCpsr =
                                 cpsrWriteByInstr(Cpsr | CondCodes,
-                                                 rotated_imm, RN, false);
+                                                 rotated_imm, RN, false, sctlr.nmfi);
                             Cpsr = ~CondCodesMask & newCpsr;
                             CondCodes = CondCodesMask & newCpsr;
                 }});
-- 
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