From ef0490081fa7ebcda2e1c7adccb05b3a14014cf1 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 13 Oct 2017 10:03:14 +0100 Subject: arm: Add support for armv8 CRC32 instructions This patch introduces the ARM A32/T32/A64 CRC Instructions, which are mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as follows: 1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32 2) The instructions support predication in Aarch32 3) Using R15(PC) as source/dest operand is permitted in Aarch32 Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-by: Nikos Nikoleris Reviewed-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/5521 Maintainer: Andreas Sandberg --- src/arch/arm/isa/decoder/arm.isa | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/arch/arm/isa/decoder') diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index f0c0dec18..9b8b37a9c 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2013 ARM Limited +// Copyright (c) 2010-2013,2017 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -72,6 +72,7 @@ format DataOp { 0x3: decode OPCODE { 0x9: ArmBlxReg::armBlxReg(); } + 0x4: Crc32::crc32(); 0x5: ArmSatAddSub::armSatAddSub(); 0x6: ArmERet::armERet(); 0x7: decode OPCODE_22 { -- cgit v1.2.3