From 2a2c66c16c659af4c3588b6c1646d55c66ad53fe Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 10 Nov 2017 15:35:26 +0000 Subject: arch-arm: Fix MSR/MRS disassemble This patch is fixing the Aarch64 MSR/MRS disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the system register name Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/5861 Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/isa/formats/aarch64.isa | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/arch/arm/isa/formats/aarch64.isa') diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 2c33e2441..d640caf09 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -369,12 +369,13 @@ namespace Aarch64 return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss); if (read) { - StaticInstPtr si = new Mrs64(machInst, rt, (IntRegIndex) miscReg, iss); + StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss); if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) si->setFlag(StaticInst::IsUnverifiable); return si; - } else - return new Msr64(machInst, (IntRegIndex) miscReg, rt, iss); + } else { + return new Msr64(machInst, miscReg, rt, iss); + } } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { std::string full_mnem = csprintf("%s %s", read ? "mrs" : "msr", miscRegName[miscReg]); -- cgit v1.2.3