From 803a8db53aae57d42bd2465c9284df91ed5e7641 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 14 Feb 2018 17:45:38 +0000 Subject: arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly This patch fixes the disassembly of AArch64 Exception Generating instructions, which were not printing the encoded immediate field. This has been accomplished by changing their underlying type to a newly defined one. Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/8368 Maintainer: Andreas Sandberg --- src/arch/arm/isa/formats/aarch64.isa | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'src/arch/arm/isa/formats/aarch64.isa') diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index f39a1a5b9..68f600698 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -242,21 +242,25 @@ namespace Aarch64 (ConditionCode)(uint8_t)(bits(machInst, 3, 0)); return new BCond64(machInst, imm, condCode); } else if (bits(machInst, 25, 24) == 0x0) { + if (bits(machInst, 4, 2)) return new Unknown64(machInst); + + auto imm16 = bits(machInst, 20, 5); uint8_t decVal = (bits(machInst, 1, 0) << 0) | (bits(machInst, 23, 21) << 2); + switch (decVal) { case 0x01: - return new Svc64(machInst); + return new Svc64(machInst, imm16); case 0x02: - return new Hvc64(machInst); + return new Hvc64(machInst, imm16); case 0x03: - return new Smc64(machInst); + return new Smc64(machInst, imm16); case 0x04: - return new Brk64(machInst); + return new Brk64(machInst, imm16); case 0x08: - return new Hlt64(machInst); + return new Hlt64(machInst, imm16); case 0x15: return new FailUnimplemented("dcps1", machInst); case 0x16: -- cgit v1.2.3