From ef0490081fa7ebcda2e1c7adccb05b3a14014cf1 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 13 Oct 2017 10:03:14 +0100 Subject: arm: Add support for armv8 CRC32 instructions This patch introduces the ARM A32/T32/A64 CRC Instructions, which are mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as follows: 1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32 2) The instructions support predication in Aarch32 3) Using R15(PC) as source/dest operand is permitted in Aarch32 Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-by: Nikos Nikoleris Reviewed-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/5521 Maintainer: Andreas Sandberg --- src/arch/arm/isa/formats/aarch64.isa | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/arch/arm/isa/formats/aarch64.isa') diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 38e5b15a0..2c33e2441 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -1202,6 +1202,22 @@ namespace Aarch64 return new Asrv64(machInst, rdzr, rn, rm); case 0xb: return new Rorv64(machInst, rdzr, rn, rm); + case 0x10: + return new Crc32b64(machInst, rdzr, rn, rm); + case 0x11: + return new Crc32h64(machInst, rdzr, rn, rm); + case 0x12: + return new Crc32w64(machInst, rdzr, rn, rm); + case 0x13: + return new Crc32x64(machInst, rdzr, rn, rm); + case 0x14: + return new Crc32cb64(machInst, rdzr, rn, rm); + case 0x15: + return new Crc32ch64(machInst, rdzr, rn, rm); + case 0x16: + return new Crc32cw64(machInst, rdzr, rn, rm); + case 0x17: + return new Crc32cx64(machInst, rdzr, rn, rm); default: return new Unknown64(machInst); } -- cgit v1.2.3