From f94f70237dfaac86c83dfbb7cb24e6a821b867eb Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 9 May 2018 17:52:37 +0100 Subject: arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg --- src/arch/arm/isa/formats/aarch64.isa | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/arch/arm/isa/formats/aarch64.isa') diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 00bd0770f..722cd7415 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -377,6 +377,20 @@ namespace Aarch64 return new FailUnimplemented(read ? "mrs" : "msr", machInst, full_mnemonic); + } else if (miscReg == MISCREG_IMPDEF_UNIMPL) { + auto full_mnemonic = + csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", + read ? "mrs" : "msr", + op0, op1, crn, crm, op2); + + if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { + return new WarnUnimplemented(read ? "mrs" : "msr", + machInst, full_mnemonic + " treated as NOP"); + } else { + return new FailUnimplemented(read ? "mrs" : "msr", + machInst, full_mnemonic); + } + } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { if (miscReg == MISCREG_NZCV) { if (read) -- cgit v1.2.3