From 48525f581c6233b8f7a8a872c5774d4e245f431c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 8 Nov 2009 02:08:40 -0800 Subject: ARM: Split the condition codes out of the CPSR. This allows those bits to be renamed while allowing the other fields to control the behavior of the processor. --- src/arch/arm/isa/formats/branch.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/isa/formats/branch.isa') diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index 95f4f14e1..5f1b541ff 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -52,7 +52,7 @@ def format Branch(code,*opt_flags) {{ else: inst_flags += ('IsCondControl', ) - icode = 'if (testPredicate(Cpsr, condCode)) {\n' + icode = 'if (testPredicate(CondCodes, condCode)) {\n' icode += code icode += ' NPC = NPC + 4 + disp;\n' icode += '} else {\n' @@ -90,7 +90,7 @@ def format BranchExchange(code,*opt_flags) {{ #Condition code - icode = 'if (testPredicate(Cpsr, condCode)) {\n' + icode = 'if (testPredicate(CondCodes, condCode)) {\n' icode += code icode += ' NPC = Rm & 0xfffffffe; // Masks off bottom bit\n' icode += '} else {\n' -- cgit v1.2.3