From dd44f6bdff37fbd15a135da4d6a5b0fcf1ef2957 Mon Sep 17 00:00:00 2001
From: Matt Horsnell <matt.horsnell@arm.com>
Date: Wed, 11 Apr 2018 14:08:45 +0100
Subject: arch-arm: AArch32 Crypto SHA

This patch implements the AArch32 secure hashing instructions
from the Crypto extension.

Change-Id: Iaba8424ab71800228a9aff039d93f5c35ee7d8e5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13247
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---
 src/arch/arm/isa/formats/fp.isa | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

(limited to 'src/arch/arm/isa/formats/fp.isa')

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 2412a1f10..26abc659f 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -606,6 +606,34 @@ let {{
                         }
                     }
                 }
+            } else {
+                if (u) {
+                    switch (c) {
+                      case 0x0:
+                        return new SHA256H(machInst, vd, vn, vm);
+                      case 0x1:
+                        return new SHA256H2(machInst, vd, vn, vm);
+                      case 0x2:
+                        return new SHA256SU1(machInst, vd, vn, vm);
+                      case 0x3:
+                        return new Unknown(machInst);
+                      default:
+                        M5_UNREACHABLE;
+                    }
+                } else {
+                    switch (c) {
+                      case 0x0:
+                        return new SHA1C(machInst, vd, vn, vm);
+                      case 0x1:
+                        return new SHA1P(machInst, vd, vn, vm);
+                      case 0x2:
+                        return new SHA1M(machInst, vd, vn, vm);
+                      case 0x3:
+                        return new SHA1SU0(machInst, vd, vn, vm);
+                      default:
+                        M5_UNREACHABLE;
+                    }
+                }
             }
             return new Unknown(machInst);
           case 0xd:
@@ -1534,6 +1562,12 @@ let {{
                     return decodeNeonSTwoMiscReg<NVcltD, NVcltQ>(
                             q, size, machInst, vd, vm);
                 }
+              case 0x5:
+                if (q) {
+                    return new SHA1H(machInst, vd, vm);
+                } else {
+                    return new Unknown(machInst);
+                }
               case 0x6:
                 if (bits(machInst, 10)) {
                     if (q)
@@ -1596,6 +1630,12 @@ let {{
                 } else {
                     return new Unknown(machInst);
                 }
+              case 0x7:
+                if (q) {
+                    return new SHA256SU0(machInst, vd, vm);
+                } else {
+                    return new SHA1SU1(machInst, vd, vm);
+                }
               case 0xc:
               case 0xe:
                 if (b == 0x18) {
-- 
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