From 1344fc2668eb4ea052a96d961e91d7578c8cb054 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:05 -0500
Subject: ARM: Decode the swp and swpb instructions.

---
 src/arch/arm/isa/formats/mem.isa | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'src/arch/arm/isa/formats/mem.isa')

diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 13309ec9b..2ea45733b 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -213,6 +213,28 @@ def format AddrMode3() {{
     decode_block = decode % subs
 }};
 
+def format ArmSyncMem() {{
+    decode_block = '''
+    {
+        const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+        const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+        const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+        switch (PUBWL) {
+          case 0x10:
+            return new Swp(machInst, rt, rt2, rn);
+          case 0x14:
+            return new Swpb(machInst, rt, rt2, rn);
+          case 0x18:
+            return new WarnUnimplemented("strex", machInst);
+          case 0x19:
+            return new WarnUnimplemented("ldrex", machInst);
+          default:
+            return new Unknown(machInst);
+        }
+    }
+    '''
+}};
+
 def format Thumb32LoadWord() {{
     decode = '''
     {
-- 
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