From 6fb5189c47546fe97fb66550f5484f4d96c4397b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:10 -0500 Subject: ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers. --- src/arch/arm/isa/formats/misc.isa | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/arch/arm/isa/formats/misc.isa') diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 8d386b0b0..d01b5014d 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -128,6 +128,15 @@ def format McrMrc15() {{ case MISCREG_BPIALL: return new WarnUnimplemented( isRead ? "mrc bpiall" : "mcr bpiall", machInst); + case MISCREG_DRBAR: + return new WarnUnimplemented( + isRead ? "mrc drbar" : "mcr drbar", machInst); + case MISCREG_DRACR: + return new WarnUnimplemented( + isRead ? "mrc dracr" : "mcr dracr", machInst); + case MISCREG_DRSR: + return new WarnUnimplemented( + isRead ? "mrc drsr" : "mcr drsr", machInst); default: if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); -- cgit v1.2.3