From 9900629f83139ed213a440375ea32bc95333b8d9 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 29 Oct 2014 23:18:24 -0500 Subject: arm: Mark some miscregs (timer counter) registers at unverifiable. The checker can't verify timer registers, so it should just grab the version from the executing CPU, otherwise it could get a larger value and diverge execution. --- src/arch/arm/isa/formats/misc.isa | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/isa/formats/misc.isa') diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 925ed55cd..f81b96f2f 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -273,8 +273,12 @@ let {{ if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1); - if (isRead) - return new Mrrc15(machInst, miscReg, rt2, rt, iss); + if (isRead) { + StaticInstPtr si = new Mrrc15(machInst, miscReg, rt2, rt, iss); + if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) + si->setFlag(StaticInst::IsUnverifiable); + return si; + } return new Mcrr15(machInst, rt2, rt, miscReg, iss); } else { return new FailUnimplemented(isRead ? "mrrc" : "mcrr", machInst, -- cgit v1.2.3