From 358fdc2a40e8a455f508532b47e55f3252053805 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:17 -0500 Subject: ARM: Decode to specialized conditional/unconditional versions of instructions. This is to avoid condition code based dependences from effectively serializing instructions when the instruction doesn't actually use them. --- src/arch/arm/isa/formats/pred.isa | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/arch/arm/isa/formats') diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index 897edc2dc..18df8491c 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -150,10 +150,10 @@ def format DataOp(code, flagtype = logic) {{ "predicate_test": predicateTest}) regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp', {"code": regCode + regCcCode, - "predicate_test": predicateTest}) + "predicate_test": condPredicateTest}) immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp', {"code": immCode + immCcCode, - "predicate_test": predicateTest}) + "predicate_test": condPredicateTest}) header_output = BasicDeclare.subst(regIop) + \ BasicDeclare.subst(immIop) + \ BasicDeclare.subst(regCcIop) + \ @@ -176,7 +176,7 @@ def format DataImmOp(code, flagtype = logic) {{ "predicate_test": predicateTest}) ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp', {"code": code + getImmCcCode(flagtype), - "predicate_test": predicateTest}) + "predicate_test": condPredicateTest}) header_output = BasicDeclare.subst(iop) + \ BasicDeclare.subst(ccIop) decoder_output = BasicConstructor.subst(iop) + \ -- cgit v1.2.3