From 38cf6a164d7081f1a2f40ab210169681b4cd6929 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@arm.com>
Date: Mon, 23 Aug 2010 11:18:40 -0500
Subject: ARM: Implement some more misc registers

---
 src/arch/arm/isa/formats/misc.isa | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/arch/arm/isa/formats')

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 2801ebedf..884d93066 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -113,6 +113,9 @@ let {{
           case MISCREG_DCCMVAC:
             return new WarnUnimplemented(
                     isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
+          case MISCREG_DCCMVAU:
+            return new WarnUnimplemented(
+                    isRead ? "mrc dccmvau" : "mcr dccmvau", machInst);
           case MISCREG_CP15ISB:
             return new WarnUnimplemented(
                     isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);
-- 
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