From adbd84ab9fffdcdce18f564acffa508c10164c9f Mon Sep 17 00:00:00 2001 From: Matt Horsnell Date: Tue, 18 Jan 2011 16:30:05 -0600 Subject: ARM: The ARM decoder should not panic when decoding undefined holes is arch. This can abort simulations when the fetch unit runs ahead and speculatively decodes instructions that are off the execution path. --- src/arch/arm/isa/formats/fp.isa | 10 +++++++++- src/arch/arm/isa/formats/misc.isa | 5 ++++- 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/isa/formats') diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 9d40a4a43..3a0cad1c5 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -758,7 +758,15 @@ let {{ bits(machInst, 24)) << 7) | (bits(machInst, 18, 16) << 4) | (bits(machInst, 3, 0) << 0); - const uint64_t bigImm = simd_modified_imm(op, cmode, imm); + + // Check for invalid immediate encodings and return an unknown op + // if it happens + bool immValid = true; + const uint64_t bigImm = simd_modified_imm(op, cmode, imm, immValid); + if (!immValid) { + return new Unknown(machInst); + } + if (op) { if (bits(cmode, 3) == 0) { if (bits(cmode, 0) == 0) { diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index c2003fe6d..6a734a582 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -100,7 +100,10 @@ let {{ case MISCREG_NOP: return new NopInst(machInst); case NUM_MISCREGS: - return new Unknown(machInst); + return new FailUnimplemented( + csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", + crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(), + machInst); case MISCREG_DCCISW: return new WarnUnimplemented( isRead ? "mrc dccisw" : "mcr dcisw", machInst); -- cgit v1.2.3