From b27545be48f7065aa6561e5d46e8316951f5eeee Mon Sep 17 00:00:00 2001
From: Matt Horsnell <matt.horsnell@arm.com>
Date: Wed, 9 May 2018 12:40:24 +0100
Subject: arch-arm: AArch32 Crypto AES

This patch implements the AArch32 AES instructions
from the Crypto extension.

Change-Id: I51e6deda748b0c26135bcfe9d0c7128f3af91f3d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Matt Horsnell <matt.horsnell@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13248
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---
 src/arch/arm/isa/formats/fp.isa | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/arch/arm/isa/formats')

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 26abc659f..77a33e6fe 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -1476,6 +1476,18 @@ let {{
               case 0x5:
                 return decodeNeonUTwoMiscSReg<NVpaddlD, NVpaddlQ>(
                         q, size, machInst, vd, vm);
+              case 0x6:
+                if (q == 0) {
+                    return new AESE(machInst, vd, vd, vm);
+                } else {
+                    return new AESD(machInst, vd, vd, vm);
+                }
+              case 0x7:
+                if (q == 0) {
+                    return new AESMC(machInst, vd, vm);
+                } else {
+                    return new AESIMC(machInst, vd, vm);
+                }
               case 0x8:
                 return decodeNeonSTwoMiscReg<NVclsD, NVclsQ>(
                         q, size, machInst, vd, vm);
-- 
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