From d63020717c8a722eb2f5236eacd042cdee78769d Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 23 Feb 2011 15:10:48 -0600
Subject: ARM: Adds dummy support for a L2 latency miscreg.

---
 src/arch/arm/isa/formats/misc.isa | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/arch/arm/isa/formats')

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 6a734a582..3bcb5c97d 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -143,6 +143,9 @@ let {{
           case MISCREG_BPIALL:
             return new WarnUnimplemented(
                     isRead ? "mrc bpiall" : "mcr bpiall", machInst);
+          case MISCREG_L2LATENCY:
+            return new WarnUnimplemented(
+                    isRead ? "mrc l2latency" : "mcr l2latency", machInst);
 
             // Write only.
           case MISCREG_TLBIALLIS:
-- 
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