From 401165c778108ab22aeeee55c4f4451ca93bcffb Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Fri, 13 May 2011 17:27:01 -0500
Subject: ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
---
 src/arch/arm/isa/insts/fp.isa | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

(limited to 'src/arch/arm/isa/insts/fp.isa')

diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 53d0b3413..73b3aa50e 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -235,16 +235,18 @@ let {{
     decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
     exec_output += PredOpExecute.subst(vmrsFpscrIop);
 
-    vmrsApsrFpscrCode = vmrsEnabledCheckCode + '''
-        Dest = FpCondCodes & FpCondCodesMask;
+    vmrsApsrFpscrCode = vmrsApsrEnabledCheckCode + '''
+        FPSCR fpscr = FpCondCodes;
+        CondCodesNZ = (fpscr.n << 1) | fpscr.z;
+        CondCodesC = fpscr.c;
+        CondCodesV = fpscr.v;
     '''
-    vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp",
+    vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp",
                                      { "code": vmrsApsrFpscrCode,
                                        "predicate_test": predicateTest,
-                                       "op_class": "SimdFloatMiscOp" },
-                                     ["IsSerializeBefore"])
-    header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop);
-    decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop);
+                                       "op_class": "SimdFloatMiscOp" })
+    header_output += BasicDeclare.subst(vmrsApsrFpscrIop);
+    decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop);
     exec_output += PredOpExecute.subst(vmrsApsrFpscrIop);
 
     vmovImmSCode = vfpEnabledCheckCode + '''
-- 
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