From 99fafb72b87f3b63f205bee7b20b8c19724d6305 Mon Sep 17 00:00:00 2001
From: Ali Saidi <ali.saidi@arm.com>
Date: Wed, 25 Aug 2010 19:10:42 -0500
Subject: ARM: Fix VFP enabled checks for mem instructions

---
 src/arch/arm/isa/insts/fp.isa | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'src/arch/arm/isa/insts/fp.isa')

diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 849ce1299..6ba4ac3bf 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -192,14 +192,14 @@ let {{
     exec_output = ""
 
     vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp",
-                            { "code": vmsrrsEnabledCheckCode + \
+                            { "code": vmsrEnabledCheckCode + \
                                       "MiscDest = Op1;",
                               "predicate_test": predicateTest }, [])
     header_output += FpRegRegOpDeclare.subst(vmsrIop);
     decoder_output += FpRegRegOpConstructor.subst(vmsrIop);
     exec_output += PredOpExecute.subst(vmsrIop);
 
-    vmsrFpscrCode = vmsrrsEnabledCheckCode + '''
+    vmsrFpscrCode = vmsrEnabledCheckCode + '''
     Fpscr = Op1 & ~FpCondCodesMask;
     FpCondCodes = Op1 & FpCondCodesMask;
     '''
@@ -211,7 +211,7 @@ let {{
     exec_output += PredOpExecute.subst(vmsrFpscrIop);
 
     vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp",
-                            { "code": vmsrrsEnabledCheckCode + \
+                            { "code": vmrsEnabledCheckCode + \
                                       "Dest = MiscOp1;",
                               "predicate_test": predicateTest }, [])
     header_output += FpRegRegOpDeclare.subst(vmrsIop);
@@ -219,14 +219,14 @@ let {{
     exec_output += PredOpExecute.subst(vmrsIop);
 
     vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp",
-                                 { "code": vmsrrsEnabledCheckCode + \
+                                 { "code": vmrsEnabledCheckCode + \
                                            "Dest = Fpscr | FpCondCodes;",
                                    "predicate_test": predicateTest }, [])
     header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop);
     decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
     exec_output += PredOpExecute.subst(vmrsFpscrIop);
 
-    vmrsApsrCode = vmsrrsEnabledCheckCode + '''
+    vmrsApsrCode = vmrsEnabledCheckCode + '''
         Dest = (MiscOp1 & imm) | (Dest & ~imm);
     '''
     vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp",
@@ -236,7 +236,7 @@ let {{
     decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop);
     exec_output += PredOpExecute.subst(vmrsApsrIop);
 
-    vmrsApsrFpscrCode = vmsrrsEnabledCheckCode + '''
+    vmrsApsrFpscrCode = vmrsEnabledCheckCode + '''
     assert((imm & ~FpCondCodesMask) == 0);
     Dest = (FpCondCodes & imm) | (Dest & ~imm);
     '''
-- 
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