From 2178859b76bb13b1d225fc4dffa04d43d2db2e14 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 May 2011 17:27:01 -0500 Subject: ARM: Break up condition codes into normal flags, saturation, and simd. This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags. --- src/arch/arm/isa/insts/mult.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/isa/insts/mult.isa') diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa index b3a9fca5f..b02386c63 100644 --- a/src/arch/arm/isa/insts/mult.isa +++ b/src/arch/arm/isa/insts/mult.isa @@ -44,7 +44,7 @@ let {{ exec_output = "" calcQCode = ''' - CondCodes = CondCodes | ((resTemp & 1) << 27); + CondCodesQ = CondCodesQ | ((resTemp & 1) << 27); ''' calcCcCode = ''' @@ -52,7 +52,7 @@ let {{ _in = (resTemp >> %(negBit)d) & 1; _iz = ((%(zType)s)resTemp == 0); - CondCodes = _in << 31 | _iz << 30 | (CondCodes & 0x3FFFFFFF); + CondCodesF = _in << 31 | _iz << 30 | (CondCodesF & 0x3FFFFFFF); DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz); ''' -- cgit v1.2.3