From 401165c778108ab22aeeee55c4f4451ca93bcffb Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Fri, 13 May 2011 17:27:01 -0500
Subject: ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
---
 src/arch/arm/isa/insts/mult.isa | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/arch/arm/isa/insts/mult.isa')

diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa
index 31febe747..f4f8b867e 100644
--- a/src/arch/arm/isa/insts/mult.isa
+++ b/src/arch/arm/isa/insts/mult.isa
@@ -52,7 +52,7 @@ let {{
         _in = (resTemp >> %(negBit)d) & 1;
         _iz = ((%(zType)s)resTemp == 0);
 
-        CondCodesF =  _in << 31 | _iz << 30 | (CondCodesF & 0x3FFFFFFF);
+        CondCodesNZ = (_in << 1) | _iz;
 
         DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz);
        '''
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