From 352d666fa1e9b5ae960127c95d19cf63c8ff0df7 Mon Sep 17 00:00:00 2001 From: Edmund Grimley Evans Date: Thu, 28 Jun 2018 14:32:01 +0100 Subject: arch-arm: Add FP16 support introduced by Armv8.2-A This changeset adds support for FP/SIMD instructions with half-precision floating-point operands. Change-Id: I4957f111c9c5e5d6a3747fe9d169d394d642fee8 Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/13084 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/isa/insts/neon64.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/isa/insts/neon64.isa') diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index 4897e7c91..eb130dbbd 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -1,6 +1,6 @@ // -*- mode: c++ -*- -// Copyright (c) 2012-2013, 2015-2016 ARM Limited +// Copyright (c) 2012-2013, 2015-2018 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -45,7 +45,7 @@ let {{ decoders = { 'Generic' : {} } # FP types (FP operations always work with unsigned representations) - floatTypes = ("uint32_t", "uint64_t") + floatTypes = ("uint16_t", "uint32_t", "uint64_t") smallFloatTypes = ("uint32_t",) def threeEqualRegInstX(name, Name, opClass, types, rCount, op, -- cgit v1.2.3