From bb319a589e72c006269d6f82fdfa715cc3a6caaf Mon Sep 17 00:00:00 2001
From: Matt Horsnell <Matt.Horsnell@arm.com>
Date: Wed, 23 Feb 2011 15:10:49 -0600
Subject: ARM: Mark store conditionals as such.

---
 src/arch/arm/isa/insts/swap.isa | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'src/arch/arm/isa/insts/swap.isa')

diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa
index d924f3029..6a6ac837c 100644
--- a/src/arch/arm/isa/insts/swap.isa
+++ b/src/arch/arm/isa/insts/swap.isa
@@ -46,7 +46,7 @@ let {{
         decConstBase = 'Swap'
 
         def __init__(self, name, Name, eaCode,
-                     preAccCode, postAccCode, memFlags):
+                     preAccCode, postAccCode, memFlags, instFlags = []):
             super(SwapInst, self).__init__()
             self.name = name
             self.Name = Name
@@ -54,6 +54,7 @@ let {{
             self.preAccCode = preAccCode
             self.postAccCode = postAccCode
             self.memFlags = memFlags
+            self.instFlags = instFlags
 
         def emit(self):
             global header_output, decoder_output, exec_output
@@ -61,12 +62,10 @@ let {{
                           "preacc_code": self.preAccCode,
                           "postacc_code": self.postAccCode }
             codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
-
             (newHeader,
              newDecoder,
              newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
-                                           self.memFlags,
-                                           ['IsStoreConditional'],
+                                           self.memFlags, self.instFlags,
                                            base = 'Swap')
             header_output += newHeader
             decoder_output += newDecoder
@@ -77,12 +76,14 @@ let {{
              'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);',
              ['Request::MEM_SWAP',
               'ArmISA::TLB::AlignWord',
-              'ArmISA::TLB::MustBeOne']).emit()
+              'ArmISA::TLB::MustBeOne'],
+              ['IsStoreConditional']).emit()
 
     SwapInst('swpb', 'Swpb', 'EA = Base;',
              'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);',
              'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
              ['Request::MEM_SWAP',
               'ArmISA::TLB::AlignByte',
-              'ArmISA::TLB::MustBeOne']).emit()
+              'ArmISA::TLB::MustBeOne'],
+              ['IsStoreConditional']).emit()
 }};
-- 
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