From faf6c727f6f206238eb6cbd4f6c84f6136c739a2 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:10 -0500
Subject: ARM: Respect the E bit of the CPSR when doing loads and stores.

---
 src/arch/arm/isa/insts/swap.isa | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/arch/arm/isa/insts/swap.isa')

diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa
index 9456c1314..29b5b444f 100644
--- a/src/arch/arm/isa/insts/swap.isa
+++ b/src/arch/arm/isa/insts/swap.isa
@@ -44,7 +44,8 @@ let {{
     (newHeader,
      newDecoder,
      newExec) = SwapBase("swp", "Swp", "EA = Base;",
-                         "Mem = Op1;", "Dest = memData;",
+                         "Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);",
+                         "Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);",
                          ["Request::MEM_SWAP",
                           "ArmISA::TLB::AlignWord",
                           "ArmISA::TLB::MustBeOne"], [])
@@ -55,7 +56,8 @@ let {{
     (newHeader,
      newDecoder,
      newExec) = SwapBase("swpb", "Swpb", "EA = Base;",
-                         "Mem.ub = Op1.ub;", "Dest.ub = (uint8_t)memData;",
+                         "Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);",
+                         "Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);",
                          ["Request::MEM_SWAP",
                           "ArmISA::TLB::AlignByte",
                           "ArmISA::TLB::MustBeOne"], [])
-- 
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