From 401165c778108ab22aeeee55c4f4451ca93bcffb Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 May 2011 17:27:01 -0500 Subject: ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. --- src/arch/arm/isa/insts/data.isa | 42 +++++++++++++++++++------------- src/arch/arm/isa/insts/fp.isa | 16 +++++++------ src/arch/arm/isa/insts/ldr.isa | 8 +++++-- src/arch/arm/isa/insts/macromem.isa | 40 ++++++++++++++++++------------- src/arch/arm/isa/insts/mem.isa | 31 +++++++++++++++++++++--- src/arch/arm/isa/insts/misc.isa | 48 +++++++++++++++++++++++++------------ src/arch/arm/isa/insts/mult.isa | 2 +- src/arch/arm/isa/insts/str.isa | 2 +- 8 files changed, 128 insertions(+), 61 deletions(-) (limited to 'src/arch/arm/isa/insts') diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 1a239f48b..94693c8ef 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -44,7 +44,7 @@ let {{ exec_output = "" calcGECode = ''' - CondCodesGE = insertBits(0, 19, 16, resTemp); + CondCodesGE = resTemp; ''' calcQCode = ''' @@ -58,15 +58,17 @@ let {{ _iv = %(ivValue)s & 1; _ic = %(icValue)s & 1; - CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28; + CondCodesNZ = (_in << 1) | _iz; + CondCodesC = _ic; + CondCodesV = _iv; DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n", _in, _iz, _ic, _iv); ''' # Dict of code to set the carry flag. (imm, reg, reg-reg) - oldC = 'CondCodesF<29:>' - oldV = 'CondCodesF<28:>' + oldC = 'CondCodesC' + oldV = 'CondCodesV' carryCode = { "none": (oldC, oldC, oldC), "llbit": (oldC, oldC, oldC), @@ -101,8 +103,8 @@ let {{ secondOpRe = re.compile("secondOp") immOp2 = "imm" - regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesF<29:>)" - regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesF<29:>)" + regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesC)" + regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesC)" def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ buildCc = True, buildNonCc = True, instFlags = []): @@ -238,16 +240,24 @@ let {{ if subsPcLr: code += ''' SCTLR sctlr = Sctlr; - uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, - Spsr, 0xF, true, sctlr.nmfi); - Cpsr = ~CondCodesMask & newCpsr; - CondCodesF = CondCodesMaskF & newCpsr; - CondCodesGE = CondCodesMaskGE & newCpsr; - NextThumb = ((CPSR)newCpsr).t; - NextJazelle = ((CPSR)newCpsr).j; - NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC) - | (((CPSR)newCpsr).it1 & 0x3); + CPSR old_cpsr = Cpsr; + old_cpsr.nz = CondCodesNZ; + old_cpsr.c = CondCodesC; + old_cpsr.v = CondCodesV; + old_cpsr.ge = CondCodesGE; + + CPSR new_cpsr = + cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi); + Cpsr = ~CondCodesMask & new_cpsr; + CondCodesNZ = new_cpsr.nz; + CondCodesC = new_cpsr.c; + CondCodesV = new_cpsr.v; + CondCodesGE = new_cpsr.ge; + + NextThumb = (new_cpsr).t; + NextJazelle = (new_cpsr).j; + NextItState = (((new_cpsr).it2 << 2) & 0xFC) + | ((new_cpsr).it1 & 0x3); SevMailbox = 1; ''' buildImmDataInst(mnem + 's', code, flagType, diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 53d0b3413..73b3aa50e 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -235,16 +235,18 @@ let {{ decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); exec_output += PredOpExecute.subst(vmrsFpscrIop); - vmrsApsrFpscrCode = vmrsEnabledCheckCode + ''' - Dest = FpCondCodes & FpCondCodesMask; + vmrsApsrFpscrCode = vmrsApsrEnabledCheckCode + ''' + FPSCR fpscr = FpCondCodes; + CondCodesNZ = (fpscr.n << 1) | fpscr.z; + CondCodesC = fpscr.c; + CondCodesV = fpscr.v; ''' - vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", + vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp", { "code": vmrsApsrFpscrCode, "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, - ["IsSerializeBefore"]) - header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); - decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); + "op_class": "SimdFloatMiscOp" }) + header_output += BasicDeclare.subst(vmrsApsrFpscrIop); + decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop); exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); vmovImmSCode = vfpEnabledCheckCode + ''' diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index 9211983d4..a346c495a 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -106,7 +106,11 @@ let {{ wbDiff = 8 accCode = ''' CPSR cpsr = Cpsr; - URc = cpsr | CondCodesF | CondCodesGE; + cpsr.nz = CondCodesNZ; + cpsr.c = CondCodesC; + cpsr.v = CondCodesV; + cpsr.ge = CondCodesGE; + URc = cpsr; URa = cSwap(Mem.ud, cpsr.e); URb = cSwap(Mem.ud >> 32, cpsr.e); ''' @@ -137,7 +141,7 @@ let {{ def __init__(self, *args, **kargs): super(LoadRegInst, self).__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ - " shiftType, CondCodesF<29:>)" + " shiftType, CondCodesC)" if self.add: self.wbDecl = ''' MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 8523b840c..31545d3a4 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -87,15 +87,21 @@ let {{ ['IsMicroop']) microRetUopCode = ''' - CPSR cpsr = Cpsr; + CPSR old_cpsr = Cpsr; SCTLR sctlr = Sctlr; - uint32_t newCpsr = - cpsrWriteByInstr(cpsr | CondCodesF | CondCodesGE, - Spsr, 0xF, true, sctlr.nmfi); - Cpsr = ~CondCodesMask & newCpsr; - CondCodesF = CondCodesMaskF & newCpsr; - CondCodesGE = CondCodesMaskGE & newCpsr; - IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); + old_cpsr.nz = CondCodesNZ; + old_cpsr.c = CondCodesC; + old_cpsr.v = CondCodesV; + old_cpsr.ge = CondCodesGE; + + CPSR new_cpsr = + cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi); + Cpsr = ~CondCodesMask & new_cpsr; + CondCodesNZ = new_cpsr.nz; + CondCodesC = new_cpsr.c; + CondCodesV = new_cpsr.v; + CondCodesGE = new_cpsr.ge; + IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0); NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) | (((CPSR)Spsr).it1 & 0x3); SevMailbox = 1; @@ -587,7 +593,7 @@ let {{ {'code': '''URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, - CondCodesF<29:>); + CondCodesC); ''', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -603,7 +609,7 @@ let {{ {'code': '''URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, - CondCodesF<29:>); + CondCodesC); ''', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -625,16 +631,18 @@ let {{ CPSR cpsrOrCondCodes = URc; SCTLR sctlr = Sctlr; pNPC = URa; - uint32_t newCpsr = + CPSR new_cpsr = cpsrWriteByInstr(cpsrOrCondCodes, URb, 0xF, true, sctlr.nmfi); - Cpsr = ~CondCodesMask & newCpsr; - NextThumb = ((CPSR)newCpsr).t; - NextJazelle = ((CPSR)newCpsr).j; + Cpsr = ~CondCodesMask & new_cpsr; + NextThumb = new_cpsr.t; + NextJazelle = new_cpsr.j; NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) | (((CPSR)URb).it1 & 0x3); - CondCodesF = CondCodesMaskF & newCpsr; - CondCodesGE = CondCodesMaskGE & newCpsr; + CondCodesNZ = new_cpsr.nz; + CondCodesC = new_cpsr.c; + CondCodesV = new_cpsr.v; + CondCodesGE = new_cpsr.ge; ''' microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index 0ebd34ad4..cad0b1589 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -119,10 +119,35 @@ let {{ return (header_output, decoder_output, exec_output) def pickPredicate(blobs): + opt_nz = True + opt_c = True + opt_v = True for val in blobs.values(): - if re.search('(?> %(negBit)d) & 1; _iz = ((%(zType)s)resTemp == 0); - CondCodesF = _in << 31 | _iz << 30 | (CondCodesF & 0x3FFFFFFF); + CondCodesNZ = (_in << 1) | _iz; DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz); ''' diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index 312bcac16..95ba4ad39 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -152,7 +152,7 @@ let {{ def __init__(self, *args, **kargs): super(StoreRegInst, self).__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ - " shiftType, CondCodesF<29:>)" + " shiftType, CondCodesC)" if self.add: self.wbDecl = ''' MicroAddUop(machInst, base, base, index, shiftAmt, shiftType); -- cgit v1.2.3