From 68bc5397c937c7289ad7e78416132dc77ccf34a9 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 24 Oct 2018 13:34:25 +0100 Subject: arch-arm: Refactor AArch64 MSR/MRS trapping This patch refactors AArch64 MSR/MRS trapping, by moving the trapping helpers in arch/arm/utility and in the isa code into a MiscRegOp64 class. This class is the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS. The common denominator or those instruction is the chance that the system register access is trapped to an upper Exception level. MiscRegOp64 is providing that feature. What do we gain? Other "pseudo" instructions, like access to implementation defined registers can inherit from this class to make use of the trapping functionalities even if there is no data movement between GPRs and system register. Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/13778 Maintainer: Andreas Sandberg --- src/arch/arm/isa/insts/data64.isa | 33 +++++---------------------------- 1 file changed, 5 insertions(+), 28 deletions(-) (limited to 'src/arch/arm/isa/insts') diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index 5f2a44c13..d348190ae 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -326,31 +326,8 @@ let {{ mnemonic); } - // Check for traps to supervisor (FP/SIMD regs) - if (el <= EL1 && msrMrs64TrapToSup(flat_idx, el, Cpacr64)) - return std::make_shared(machInst, 0x1E00000, - EC_TRAPPED_SIMD_FP); - - bool is_vfp_neon = false; - - // Check for traps to hypervisor - if ((ArmSystem::haveVirtualization(xc->tcBase()) && el <= EL2) && - msrMrs64TrapToHyp(flat_idx, el, %s, CptrEl264, Hcr64, - Scr64, cpsr, &is_vfp_neon)) { - - return std::make_shared( - machInst, is_vfp_neon ? 0x1E00000 : imm, - is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64); - } - - // Check for traps to secure monitor - if ((ArmSystem::haveSecurity(xc->tcBase()) && el <= EL3) && - msrMrs64TrapToMon(flat_idx, CptrEl364, el, &is_vfp_neon)) { - return std::make_shared( - machInst, - is_vfp_neon ? 0x1E00000 : imm, - is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64); - } + fault = this->trap(xc->tcBase(), flat_idx, el, imm); + if (fault != NoFault) return fault; ''' mrsCode = ''' @@ -360,7 +337,7 @@ let {{ ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; %s XDest = MiscOp1_ud; - ''' % (msrMrs64EnabledCheckCode % ('Read', 'true'),) + ''' % (msrMrs64EnabledCheckCode % ('Read'),) mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64", mrsCode, @@ -384,7 +361,7 @@ let {{ ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; %s MiscDest_ud = XOp1; - ''' % (msrMrs64EnabledCheckCode % ('Write', 'false'),) + ''' % (msrMrs64EnabledCheckCode % ('Write'),) msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64", msrCode, @@ -407,7 +384,7 @@ let {{ CPSR cpsr = Cpsr; ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; %s - ''' % (msrMrs64EnabledCheckCode % ('Write', 'false'),) + ''' % (msrMrs64EnabledCheckCode % ('Write'),) msrdczva_ea_code = msr_check_code -- cgit v1.2.3