From dbaf43394b23bbe8a3ed617d9f519a328cc8af6e Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Thu, 17 Apr 2014 16:56:09 -0500
Subject: arm: Make sure UndefinedInstructions are properly initialized

---
 src/arch/arm/isa/insts/data64.isa | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

(limited to 'src/arch/arm/isa/insts')

diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index 77d7541ca..8ec446d16 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -294,7 +294,8 @@ let {{
                 flat_idx == MISCREG_DC_CVAC_Xt ||
                 flat_idx == MISCREG_DC_CIVAC_Xt
                 )
-                return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
+                return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64,
+                                    mnemonic);
             return new UndefinedInstruction(machInst, false, mnemonic);
         }
 
@@ -396,7 +397,8 @@ let {{
         if (!canWriteAArch64SysReg(
                 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
                 Scr64, Cpsr, xc->tcBase())) {
-            return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
+            return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64,
+                            mnemonic);
         }
         CPSR cpsr = Cpsr;
         cpsr.daif = cpsr.daif | imm;
@@ -407,7 +409,8 @@ let {{
         if (!canWriteAArch64SysReg(
                 (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
                 Scr64, Cpsr, xc->tcBase())) {
-            return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
+            return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64,
+                                mnemonic);
         }
         CPSR cpsr = Cpsr;
         cpsr.daif = cpsr.daif & ~imm;
-- 
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