From f48ad5b29d6f291b4f3679ff5fb7b5beae10d6fa Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Thu, 2 Jun 2016 13:38:30 +0100 Subject: arm: Correctly check FP/SIMD access permission in aarch32 The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1 and higher are all 32-bit. This breaks interprocessing since an aarch64 EL1 uses different enable/disable bits. This change updates the permission checks to according to what is prescribed by the ARM ARM. Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88 Signed-off-by: Andreas Sandberg Reviewed-by: Mitch Hayenga Reviewed-by: Nathanael Premillieu --- src/arch/arm/isa/insts/fp.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/arm/isa/insts') diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 9a7f3f8a0..34dff5139 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -260,7 +260,7 @@ let {{ decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); exec_output += PredOpExecute.subst(vmrsFpscrIop); - vmrsApsrFpscrCode = vmrsApsrEnabledCheckCode + ''' + vmrsApsrFpscrCode = vfpEnabledCheckCode + ''' FPSCR fpscr = FpCondCodes; CondCodesNZ = (fpscr.n << 1) | fpscr.z; CondCodesC = fpscr.c; -- cgit v1.2.3