From 05866c82f9eb80db05fb423addcc8563efe1b744 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 May 2011 17:27:02 -0500 Subject: ARM: Construct the predicate test register for more instruction programatically. If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before. --- src/arch/arm/isa/operands.isa | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/arch/arm/isa/operands.isa') diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 058cc94f3..a07ee8088 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -169,6 +169,11 @@ def operands {{ '''(condCode == COND_HI || condCode == COND_LS || condCode == COND_CS || condCode == COND_CC) ? INTREG_CONDCODES_C : INTREG_ZERO'''), + 'OptShiftRmCondCodesC': intRegCC( + '''(condCode == COND_HI || condCode == COND_LS || + condCode == COND_CS || condCode == COND_CC || + shiftType == ROR) ? + INTREG_CONDCODES_C : INTREG_ZERO'''), 'OptCondCodesV': intRegCC( '''(condCode == COND_VS || condCode == COND_VC || condCode == COND_GE || condCode == COND_LT || -- cgit v1.2.3