From 05bd3eb4ec3d9fea3dbc46112a47459085d3011c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:16 -0500 Subject: ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR. --- src/arch/arm/isa/operands.isa | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/arm/isa/operands.isa') diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 4c269276a..b041cef43 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -171,6 +171,7 @@ def operands {{ 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1), + 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2), 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2), 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2), 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2), -- cgit v1.2.3