From 358fdc2a40e8a455f508532b47e55f3252053805 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:17 -0500 Subject: ARM: Decode to specialized conditional/unconditional versions of instructions. This is to avoid condition code based dependences from effectively serializing instructions when the instruction doesn't actually use them. --- src/arch/arm/isa/operands.isa | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/arm/isa/operands.isa') diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 0c52703e1..a086bb03c 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -154,6 +154,9 @@ def operands {{ 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2), 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2), + 'OptCondCodes': ('IntReg', 'uw', + '''(condCode == COND_AL || condCode == COND_UC) ? + INTREG_ZERO : INTREG_CONDCODES''', None, 2), #Register fields for microops 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite), -- cgit v1.2.3