From 4079792f2b61bd1e7c46a5aa8ddb06974982d1db Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Jul 2009 00:53:10 -0700 Subject: ARM: Add in spots for the VFP control registers. --- src/arch/arm/isa/operands.isa | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/isa/operands.isa') diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 6e6eea5a8..ac7427dad 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -82,7 +82,10 @@ def operands {{ 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40), 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41), - 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42), - 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43), + 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42), + 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43), + 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44), + 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45), + 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46) }}; -- cgit v1.2.3