From 432fa0aad6092d6a9252f6a9c83c8b36509c1341 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 8 Nov 2010 13:58:24 -0600 Subject: ARM: Add support for M5 ops in the ARM ISA --- src/arch/arm/isa/operands.isa | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/arm/isa/operands.isa') diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 8e856e74d..3c32d98d1 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -170,6 +170,9 @@ def operands {{ 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite), 'R7': ('IntReg', 'uw', '7', 'IsInteger', 3), 'R0': ('IntReg', 'uw', '0', 'IsInteger', 3), + 'R1': ('IntReg', 'uw', '0', 'IsInteger', 3), + 'R2': ('IntReg', 'uw', '1', 'IsInteger', 3), + 'Rt' : ('IntReg', 'uw', 'RT', 'IsInteger', 3, maybePCRead, maybePCWrite), 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3), 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3), -- cgit v1.2.3