From 48525f581c6233b8f7a8a872c5774d4e245f431c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 8 Nov 2009 02:08:40 -0800 Subject: ARM: Split the condition codes out of the CPSR. This allows those bits to be renamed while allowing the other fields to control the behavior of the processor. --- src/arch/arm/isa/operands.isa | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/arm/isa/operands.isa') diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 4ac6790e5..02acc8ed7 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -66,6 +66,7 @@ def operands {{ 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7), 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8), 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), + 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', 'IsInteger', 10), #Register fields for microops 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), -- cgit v1.2.3