From 769f3406fe6264353be1d3f61291c5aba6328534 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:02 -0500
Subject: ARM: Replace the interworking branch base class with a special
 operand.

---
 src/arch/arm/isa/operands.isa | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'src/arch/arm/isa/operands.isa')

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 911f0425e..3f331832c 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -60,15 +60,24 @@ let {{
         ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
          xc->%(func)s(this, %(op_idx)s, %(final_val)s))
     '''
+    maybeIWPCWrite = '''
+        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
+         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
+    '''
 
     readNPC = 'xc->readNextPC() & ~PcModeMask'
     writeNPC = 'setNextPC(xc, %(final_val)s)'
+    writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
 }};
 
 def operands {{
     #Abstracted integer reg operands
     'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
              maybePCRead, maybePCWrite),
+    'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
+               maybePCRead, maybeIWPCWrite),
+    'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
+                maybePCRead, maybeIWPCWrite),
     'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
              maybePCRead, maybePCWrite),
     'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
@@ -116,4 +125,6 @@ def operands {{
     'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
     'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
             readNPC, writeNPC),
+    'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
+              readNPC, writeIWNPC),
 }};
-- 
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