From 81fdced83f21db2fc1da1541365166fbd5918027 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:01 -0500 Subject: ARM: Define the load instructions from outside the decoder. --- src/arch/arm/isa/operands.isa | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/arch/arm/isa/operands.isa') diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index fefe9d925..f5d3e1042 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -69,6 +69,13 @@ let {{ }}; def operands {{ + #Abstracted integer reg operands + 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, + maybePCRead, maybePCWrite), + 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, + maybePCRead, maybePCWrite), + 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, + maybePCRead, maybePCWrite), #General Purpose Integer Reg Operands 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), -- cgit v1.2.3