From 98693436368ef671681859d95f6bc4a0542a6a37 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:02 -0500
Subject: ARM: Implement branch instructions external to the decoder.

---
 src/arch/arm/isa/operands.isa | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/arch/arm/isa/operands.isa')

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 3f331832c..ab4d95d47 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -68,6 +68,7 @@ let {{
     readNPC = 'xc->readNextPC() & ~PcModeMask'
     writeNPC = 'setNextPC(xc, %(final_val)s)'
     writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
+    forceNPC = 'xc->setNextPC(%(final_val)s)'
 }};
 
 def operands {{
@@ -125,6 +126,8 @@ def operands {{
     'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
     'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
             readNPC, writeNPC),
+    'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
+             readNPC, forceNPC),
     'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
               readNPC, writeIWNPC),
 }};
-- 
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