From 9d4a1bf2ba936499277b96054fbc83c478c0c6be Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:09 -0500
Subject: ARM: Explicitly keep track of the second destination for double
 loads/stores.

---
 src/arch/arm/isa/operands.isa | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

(limited to 'src/arch/arm/isa/operands.isa')

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 903982f29..0f3534385 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -90,6 +90,8 @@ def operands {{
     #Abstracted integer reg operands
     'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
              maybePCRead, maybePCWrite),
+    'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 0,
+              maybePCRead, maybePCWrite),
     'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
                maybePCRead, maybeIWPCWrite),
     'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
@@ -124,10 +126,6 @@ def operands {{
     'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
     'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
 
-    #Destination register for load/store double instructions
-    'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
-    'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
-
     'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
     'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
 
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