From a679cd917ac4775979e23594de52f1bca407c08c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 4 Apr 2011 11:42:28 -0500 Subject: ARM: Cleanup implementation of ITSTATE and put important code in PCState. Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects. --- src/arch/arm/isa/operands.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/isa/operands.isa') diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 20ce6df52..49a860213 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -217,7 +217,6 @@ def operands {{ #Fixed index control regs 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), - 'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'), 'Spsr': cntrlRegNC('MISCREG_SPSR'), 'Fpsr': cntrlRegNC('MISCREG_FPSR'), 'Fpsid': cntrlRegNC('MISCREG_FPSID'), @@ -247,7 +246,8 @@ def operands {{ 'Thumb': pcStateReg('thumb', srtPC), 'NextThumb': pcStateReg('nextThumb', srtMode), 'NextJazelle': pcStateReg('nextJazelle', srtMode), - 'ForcedItState': pcStateReg('forcedItState', srtMode), + 'NextItState': pcStateReg('nextItstate', srtMode), + 'Itstate': pcStateReg('itstate', srtMode), #Register operands depending on a field in the instruction encoding. These #should be avoided since they may not be portable across different -- cgit v1.2.3