From ac650199eeb62bf05fec11a4f2d7666cbd31331c Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Mon, 4 Apr 2011 11:42:28 -0500
Subject: ARM: Fix m5op parameters bug.

All the m5op parameters are 64 bits, but we were only sending 32 bits;
and the static register indexes were incorrectly specified.
---
 src/arch/arm/isa/operands.isa | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/arch/arm/isa/operands.isa')

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 7b014acd0..20ce6df52 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -149,9 +149,11 @@ def operands {{
     'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
     'LR': intRegNPC('INTREG_LR'),
     'R7': intRegNPC('7'),
+    # First four arguments are passed in registers
     'R0': intRegNPC('0'),
-    'R1': intRegNPC('0'),
-    'R2': intRegNPC('1'),
+    'R1': intRegNPC('1'),
+    'R2': intRegNPC('2'),
+    'R3': intRegNPC('3'),
 
     #Pseudo integer condition code registers
     'CondCodes': intRegCC('INTREG_CONDCODES'),
-- 
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