From c02f9cdddf157b91ca3a338bbe8b2a2b68d4ee93 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:02 -0500 Subject: ARM: Add new base classes for data processing instructions. --- src/arch/arm/isa/operands.isa | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/arch/arm/isa/operands.isa') diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index f5d3e1042..244d217ce 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -76,6 +76,12 @@ def operands {{ maybePCRead, maybePCWrite), 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, maybePCRead, maybePCWrite), + 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, + maybePCRead, maybePCWrite), + 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, + maybePCRead, maybePCWrite), + 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, + maybePCRead, maybePCWrite), #General Purpose Integer Reg Operands 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), -- cgit v1.2.3