From e097c4fb188fafc9cd2253500ab2d056da886c9c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 May 2011 17:27:01 -0500 Subject: ARM: Remove the saturating (Q) condition code from the renamed register. Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit. --- src/arch/arm/isa/operands.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/arm/isa/operands.isa') diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 9053f6e92..ead058b4c 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -157,7 +157,6 @@ def operands {{ #Pseudo integer condition code registers 'CondCodesF': intRegCC('INTREG_CONDCODES_F'), - 'CondCodesQ': intRegCC('INTREG_CONDCODES_Q'), 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'), 'OptCondCodesF': intRegCC( '''(condCode == COND_AL || condCode == COND_UC) ? @@ -219,6 +218,7 @@ def operands {{ #Fixed index control regs 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), + 'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr), 'Spsr': cntrlRegNC('MISCREG_SPSR'), 'Fpsr': cntrlRegNC('MISCREG_FPSR'), 'Fpsid': cntrlRegNC('MISCREG_FPSID'), -- cgit v1.2.3